1. Field of the Invention
The present invention relates generally to methods for fabricating split gate field effect transistor (FET) devices, as employed within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for fabricating, with enhanced properties, split gate field effect transistor (FET) devices, as employed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
In addition to conventional semiconductor integrated circuit microelectronic fabrications having formed therein conventional field effect transistor (FET) devices and conventional bipolar junction transistor (BJT) devices whose transient operation provides for data storage and transduction capabilities within the conventional semiconductor integrated circuit microelectronic fabrications, there also exists within the art of semiconductor integrated circuit microelectronic fabrication non-volatile semiconductor integrated circuit microelectronic fabrications, and in particular non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrically erasable programable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, whose data storage and transduction capabilities are not predicated upon transient operation.
Although non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrical erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, may be fabricated while employing any of several semiconductor integrated circuit microelectronic devices, a particularly common semiconductor integrated circuit microelectronic device employed within an electrically erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrication is a split gate field effect transistor (FET) device.
A split gate field effect transistor (FET) device is in part analogous in structure and operation with a conventional field effect transistor (FET) device insofar as a split gate field effect transistor (FET) device also comprises formed within a semiconductor substrate a channel region defined by a pair of source/drain regions also formed within the semiconductor substrate, wherein at least the channel region of the semiconductor substrate has formed thereupon a gate dielectric layer which separates a gate electrode from the channel region of the semiconductor substrate, but a split gate field effect transistor (FET) device is nonetheless distinguished from a conventional field effect transistor (FET) device by employing rather than a single gate electrode positioned upon the gate dielectric layer and completely covering the channel region of the semiconductor substrate: (1) a floating gate electrode positioned upon the gate dielectric layer (which in part serves as a tunneling dielectric layer) and covering over only a portion of the channel region defined by the pair of source/drain regions (such portion of the channel region also referred to as a floating gate electrode channel region); and (2) a control gate electrode positioned over the gate dielectric layer and covering a remainder portion of the channel region while at least partially covering and overlapping the floating gate electrode while being separated from the floating gate electrode by an inter-gate electrode dielectric layer (such remainder portion of the channel region also referred to as a control gate electrode channel region).
In order to effect operation of a split gate field effect transistor (FET) device, particular sets of voltages are applied to the control gate electrode, the source/drain regions and the semiconductor substrate in order to induce, reduce or sense charge within the floating gate electrode (which is otherwise fully electrically isolated) and thus provide conditions under which the floating gate electrode within the split gate field effect transistor (FET) device may be programmed, erased and/or read.
While split gate field effect transistor (FET) devices are thus desirable within the art of semiconductor integrated circuit microelectronic fabrication for providing semiconductor integrated circuit microelectronic fabrications with non-volatile data storage characteristics, split gate field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within non-volatile semiconductor integrated circuit microelectronic fabrications split gate field effect transistor (FET) devices with enhanced properties, such as but not limited to decreased dimensions and enhanced coupling, insofar as split gate field effect transistor (FET) devices are formed employing a plurality of microelectronic layers which may not otherwise be optimally registered with respect to each other.
It is thus towards the goal of providing for use within semiconductor integrated circuit microelectronic fabrications, and in particular within semiconductor integrated circuit microelectronic memory fabrications, split gate field effect transistor (FET) devices with enhanced properties that the present invention is directed.
Various non-volatile semiconductor integrated circuit microelectronic devices having desirable properties, and methods for fabrication thereof, have been disclosed within the art of non-volatile semiconductor integrated circuit microelectronic fabrication.
Included among the non-volatile semiconductor integrated circuit microelectronic devices and methods for fabrication thereof, but not limited among the non-volatile semiconductor integrated circuit microelectronic devices and methods for fabrication thereof, are non-volatile semiconductor integrated circuit microelectronic devices and methods for fabrication thereof as disclosed within: (1) Hong, in U.S. Pat. No. 5,427,968 (a split gate field effect transistor (FET) device and method for fabrication thereof which employs a pair of separated and self-aligned tunneling dielectric layers in conjunction with an annular shaped floating gate electrode, such as to provide for increased programming/erasing cycling within the split gate field effect transistor (FET) device); (2) Odanaka et al., in U.S. Pat. No. 6,051,860 (a non-volatile semiconductor integrated circuit microelectronic device and method for fabrication thereof which employs a stepped topographic channel region having a non-uniform dopant concentration therein, in order to provide for enhanced electron injection into a floating gate formed over the stepped topographic channel region); and (3) Kerber, in U.S. Pat. No. 6,157,060 (a split gate field effect transistor (FET) device and method for fabrication thereof which employs a pillar shaped channel region having formed surrounding thereupon an annular shaped floating gate electrode such as to provide the split gate field effect transistor (FET) device with enhanced density).
Desirable within the art of non-volatile semiconductor integrated circuit microelectronic fabrication, and in particular within the art of non-volatile semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for forming split gate field effect transistor (FET) devices with enhanced properties.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device.
A second object of the present invention is to provide the split gate field effect transistor (FET) device and the method for fabricating the split gate field effect transistor (FET) device in accord with the first object of the present invention, wherein the split gate field effect transistor (FET) device is fabricated with enhanced properties.
A third object of the present invention is to provide the split gate field effect transistor (FET) device and the method for fabricating the split gate field effect transistor (FET) device in accord with the first object of the present invention and the second object of the present invention, wherein the method for fabricating the split gate field effect transistor (FET) device is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device. To practice the method of the present invention, there is first provided a semiconductor substrate having formed therein a pair of isolation regions which bound a pair of opposite sides of an active region of the semiconductor substrate. There is then formed upon the active region of the semiconductor substrate a tunneling dielectric layer. There is then forming upon the tunneling dielectric layer and spanning over the pair of isolation regions an annular shaped floating gate electrode defining a central open annular region. There is then formed upon the floating gate electrode an inter-gate electrode dielectric layer. There is then formed upon the inter-gate electrode dielectric layer and filling the central open annular region a control gate electrode. There is then formed into the semiconductor substrate adjacent a pair of opposite edges of the floating gate electrode not bounded by the pair of isolation regions a pair of source/drain regions. Within the present invention, at least one of: (1) the annular shaped floating gate electrode is formed with a spacer shaped cross-section having a tip at its upper outer periphery; and (2) the pair of source/drain regions is formed with one of the pair of source/drain regions formed further beneath the annular shaped floating gate electrode than the other of the pair of source/drain regions.
The method for fabricating the split gate field effect transistor (FET) device in accord with the present invention contemplates the split gate field effect transistor (FET) device fabricated in accord with the method for fabricating the split gate field effect transistor (FET) device in accord with the present invention.
The present invention provides a method for fabricating within a semiconductor integrated circuit microelectronic fabrication, and in particular within a non-volatile semiconductor integrated circuit microelectronic memory fabrication, a split gate field effect transistor (FET) device, along with the split gate field effect transistor (FET) device fabricated employing the method, wherein the split gate field effect transistor (FET) device is fabricated with enhanced properties.
The present invention realizes the foregoing objects by employing within a split gate field effect transistor (FET) device comprising: (1) an annular shaped floating gate electrode formed upon a tunneling dielectric layer in turn formed upon an active region of a semiconductor substrate bounded at a pair of opposite sides by a pair of isolation regions over which also spans the annular floating gate electrode; and (2) a pair of source/drain regions formed within the active region of the semiconductor substrate adjacent a pair of opposite sides of the annular shaped floating gate electrode but not bounded by the pair of isolation regions, at least one of: (1) the annular shaped floating gate electrode formed with a spacer shaped cross-section having a tip at its upper outer periphery; and (2) the pair of source/drain regions formed with one of the pair of source/drain regions formed further beneath the annular shaped floating gate electrode than the other of the pair of source/drain regions.
The method of the present invention is readily commercially implemented. A split gate field effect transistor (FET) device fabricated in accord with the present invention may be fabricated employing methods and materials as are generally known in the art of semiconductor integrated circuit microelectronic fabrication, including but not limited to non-volatile semiconductor integrated circuit microelectronic memory fabrication, but employed within the context of a novel ordering and sequencing of process steps to provide a split gate field effect transistor (FET) device, and method for fabrication thereof, in accord with the present invention. Since it is thus a novel ordering and sequencing of process steps which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.